The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventor(s), to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
In computing systems, processors can be designed to work on several instructions simultaneously in order to boost performance. Instruction set architectures (ISAs) determine how instructions are to be executed by the processor. Typically, ISAs allow the execution of instructions in parallel if the results of executing the instructions in parallel are indistinguishable from the results if the instructions are executed serially. One complication of this is that a system has to wait to service an asynchronous event, commonly referred to as an interrupt, until all currently processing instructions have completed or can be safely prevented from completion. Consequently, the more instructions in execution simultaneously, the higher the performance of the processor. But there is a corresponding increase in the time it takes to complete these instructions before an interrupt can be serviced. The delay in executing the interrupt can adversely affect the performance of the processor in certain applications.